Semiconductor device and interconnect substrate

ABSTRACT

A semiconductor device includes a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon. The interconnect substrate includes a first main surface formed with a plurality of electrodes connected electrically to the semiconductor chip, a second main surface opposing the first main surface, and an interconnect region interposed between the first main surface and the second main surface. The electrodes include a plurality of first electrodes and second electrodes arranged orderly for receiving supply of signals. The first electrodes for signal and the second electrodes are disposed being dispersed in the arrangement thereof, and the interconnect region includes a core substrate, a plurality of interconnect layers formed on both surfaces of the core substrate respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation application of U.S. patentapplication Ser. No. 14/242,462, filed on Apr. 1, 2014, which is basedupon and claims the benefit of the prior filed Japanese PatentApplication No. 2013-081064, filed on Apr. 9, 2013, the entire contentsof which are hereby incorporated by reference.

The disclosure of Japanese Patent Application No. 2013-081064 filed onApr. 9, 2013 including the specification, drawings, and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and aninterconnect substrate and it particularly relates to a technique whichis effective when applied to a semiconductor device capable of highspeed communication.

In recent years, a communication speed in network communication has beenincreased more and a signal transmission speed exceeding 10 Gbps hasbeen used generally in network equipment. Accordingly, signal reflectionby parasitic capacitance of interface buffers (I/O devices) ofcommunication semiconductor devices (LSI: large scale integratedcircuits) mounted on the network equipment deteriorates signal quality,which imposes a significant problem. This is considered to beattributable to that the admittance of the parasitic capacitanceincreases more as the operation frequency of the I/O device is higher,which greatly lowers the input/output impedance of the I/O device toresult impedance mismatching between the I/O device and the signaltransmission line. For example, it is assumed a case that an I/O devicehaving a parasitic capacitance on the output side and an I/O devicehaving a parasitic capacitance on the input side are connected by way ofa signal transmission line having a characteristic impedance of 50Ω. Inthis case, even when each of the input resistance of the I/O device onthe input side and the output resistance of the I/O device on the outputside is defined theoretically at 50Ω, the admittance of the parasiticcapacitance of the I/O device on the input side and that on the outputside increase as the frequency of the transmitted signal is higher,which lowers the input impedance of the I/O device on the input side andthe output impedance of the I/O device on the output side. For example,when the parasitic capacitance of the I/O device on the input side andthat on the output side is 1 pF, the input/output impedance of each ofthe I/O devices is about 45Ω at 1.25 GHz, about 25Ω at 3.2 GHz(corresponding to 6.4 Gbps), and about 14Ω at 5.0 GHz (corresponding 10Gbps). Lowering of the input/output impedance of the I/O device causesremarkable impedance mismatching between the signal transmission lineand the I/O device to greatly distort the signal waveform.

For mitigating the effect of the parasitic capacitance of the I/Odevice, it has been known so far a technique of forming an impedancematching circuit on a semiconductor chip in which the I/O device isformed, or burying an inductor (L), a capacitor (C), and a resistor (R)in an interconnect substrate of a semiconductor substrate (packagingsubstrate) for mounting the semiconductor chip, thereby compensating theimpedance mismatching. In addition, an existent technique of decreasingthe distortion of the waveform caused by impedance mismatching isdisclosed as a relevant technique, for example, in Japanese PatentLaid-Open Nos. 2006-49645 and 2012-209340. Japanese Unexamined PatentApplication Publication No. 2006-49645 discloses a configuration ofdisposing plural through holes for grounding interconnect around asignal through hole in a printed substrate. Japanese Unexamined PatentApplication Publication No. 2012-209340 discloses a configuration of asignal transmission line which is formed including through via holes(through holes) for connecting an outer layer pattern and an inner layerpattern of a multilayer substrate where buried via holes are disposed ata position adjacent to the through via hole with an insulator being putbetween them.

SUMMARY

However, the method of forming the impedance matching circuit over thesemiconductor device described above involves a problem of increasingthe area of the semiconductor chip. Particularly, when signals inmultiple channels are used, since a matching circuit is necessary forevery I/O device of each channel, this remarkably increases the chiparea and is not practical. Further, the method of burying the inductor,the capacitor, or the like in the interconnect substrate of thesemiconductor package involves a problem that manufacture of theinterconnect substrate is difficult to increase the cost.

Prior to the filing of the present application, the present inventorshave studied on the formation of an impedance matching circuit in aninterconnect substrate of a semiconductor package by utilizing a throughhole in the interconnect substrate. Specifically, a through via thatforms a parasitic capacitance as the impedance matching circuit isdisposed at a position spaced apart from the I/O terminal end by λ/4 ofthe signal frequency to a signal transmission line connected to the I/Odevice on the interconnect substrate. In this configuration, a signalinputted to the I/O device is reflected by the parasitic capacitance ofthe I/O device terminal and the reflection wave is reflected again bythe parasitic capacitance of the through hole and returned beingdisplaced by λ/2 in view of the phase to the I/O device terminal end. Asa result, the reflection wave reflected by the parasitic capacitance ofthe I/O terminal and the reflection wave reflected by the parasiticcapacitance of the through hole are offset to each other to improve thesignal characteristics (for example, return loss characteristic) ofsignals in the signal transmission line.

When the technique described above is applied to a semiconductor devicethat uses signals of multiple channels, since the through hole as animpedance matching circuit is formed for every signal transmission lineof each channel, a wide region is required for forming plural throughholes to the interconnect substrate. Particularly, in a case of adifferential signal line pair, since through holes connected to a groundpotential have to be disposed so as to surround the through hole as theimpedance matching circuit connected to the differential signal line inorder to propagate the differential signals from the upper layer to thelower layer a wide region is required on the interconnect substrate.However, in a semiconductor device encapsulating plural semiconductorchips in one semiconductor package such as SiP (system in a package),since the interconnect density or the via density of the packagingsubstrate are high, it is not easy to ensure a sufficient region to formthe through holes described above. For example, in a SiP where pluralsemiconductor chips are mounted, interconnects, through holes, and viasfor electrically connecting the semiconductor chips to each other areformed densely in a region between one semiconductor chip and anothersemiconductor chip connected therewith (for example, in a central areaof the interconnect substrate). On the other hand, interconnects,through holes, and vias for connecting a semiconductor chip and anexternal terminal (external bump) (for example, interconnects, vias,etc. for electrically connecting I/O devices on the semiconductor chipand external bumps) are densely formed to the outer periphery of thesemiconductor chip in the packaging substrate, that is, in a narrow areafrom the end of the semiconductor chip to the end of the packagingsubstrate. When the through holes as the impedance matching circuits aredisposed in the signal transmission line for connecting the I/O deviceand the external bump, since they have to be formed in the narrow regionas described above, it becomes more difficult to ensure a region forforming the through holes as the number of I/O devices increases.Particularly, when most of the I/O devices transmit signals in anidentical frequency band, since the through holes are formed densely atpositions of an identical distance from the I/O terminal end (forexample, positions spaced apart by λ/4 of the signal frequency),arrangement of the interconnects (routing) is difficult. Accordingly, itis necessary to provide a countermeasure such as increase of the size ofthe packaging substrate to result in increase of the manufacturing cost.The techniques of Japanese Unexamined Patent Application PublicationNos. 2006-049645 and 2012-209340 are adapted to control the parasiticcapacitance (impedance) of the through hole included in the signaltransmission line but not to positively dispose the through holes in thesignal transmission line for improving the signal characteristics and noparticular consideration is made for ensuring a region for disposingplural through holes.

Means for solving such subjects are to be described below. Othersubjects and novel features will become apparent in view of thedescription of the specification and the appended drawings.

The outline of typical embodiments among those disclosed in the presentinvention will be simply described below.

According to an aspect of the present invention, a semiconductor devicehas a semiconductor chip and an interconnect substrate in which thesemiconductor chips are mounted. The interconnect substrate has a firstmain surface in which plural first electrodes connected electrically tothe semiconductor chip, a second main surface opposing the first mainsurface, and an interconnect region interposed between the first mainsurface and the second main surface. The first electrode includes pluralfirst signal electrodes and second signal electrodes disposed orderlyfor receiving supply of signals at a predetermined frequency. The firstsignal electrodes and the second signal electrodes are disposed beingdispersed in the arrangement thereof. The interconnect region has a coresubstrate, plural interconnect layers formed respectively on bothsurfaces of the core substrate, and plural first through holes that passthrough the core substrate for forming an impedance matchingcapacitances. The interconnect region further has plural first vias thatpass through the interconnect layer formed to the core substrate on theside of the first main surface for forming impedance matchingcapacitances. The interconnect region further includes plural firstsignal interconnects connected to the corresponding first signalelectrodes and plural second signal interconnects connected to thecorresponding second signal electrodes.

The first through hole is connected to the first signal interconnect ata position spaced apart from the first signal electrode by a firstinterconnect length, and the first via is connected to the second signalinterconnect at a position spaced apart from the second signal electrodeby a second interconnect length substantially equal with the firstinterconnect length.

Advantageous effects obtained by typical embodiments, among thosedisclosed in the present application will be simply described below.

According to the aspect of the invention, the semiconductor device mayattain good signal transmission characteristics while suppressing amanufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an entire schematic cross sectional view of an electroniccircuit in which a semiconductor device according to an embodiment ofthe invention is mounted;

FIG. 2 is a detailed entire schematic cross sectional view of thesemiconductor device;

FIG. 3 is a view illustrating a connection relation between thesemiconductor device and another semiconductor device;

FIG. 4 is a view illustrating matching circuits formed in a packagingsubstrate of the semiconductor device;

FIG. 5A is a graph showing signal characteristics when a matchingcircuit CT1 is disposed to a transmission line SNT1;

FIG. 5B is a graph showing signal characteristics when matching circuitsCT1 and CT2 are disposed to a transmission line SNP1;

FIG. 6 is a schematic view illustrating a matching circuit formed to apackaging substrate;

FIG. 7A shows an example of a first shape of a land connected to athrough hole for forming a matching circuit;

FIG. 7B shows an example of a second shape of the land connected to thethrough hole for forming a matching circuit;

FIG. 7C shows an example of a third shape of the land connected to thethrough hole for forming the matching circuit;

FIG. 8A shows an example of a first shape of a land of a via for forminga matching circuit;

FIG. 8B shows an example of a second shape of the land of the via forforming the matching circuit;

FIG. 8C shows an example of a third shape of the land of the via forforming the matching circuit; and

FIG. 8D shows an example of a fourth shape of the land of the via forforming the matching circuit;

FIG. 9 is a plan view of the semiconductor device;

FIG. 10 is a schematic cross sectional view of the packaging substratein which through holes and vias as matching circuits are formed;

FIG. 11A shows a first connection example of an interconnect to a viafor forming a matching circuit;

FIG. 11B shows a second connection example of the interconnect to thevia for forming the matching circuit; and

FIG. 11C shows a third connection example of the interconnect to the viafor forming the matching circuit;

FIG. 12 is a plan view illustrating an interconnect layer: Layer 2;

FIG. 13 is a plan view illustrating an interconnect layer: Layer 4;

FIG. 14 is a plan view illustrating an interconnect layer: Layer 5;

FIG. 15 is a plan view illustrating an interconnect layer: Layer 6;

FIG. 16 is a plan view illustrating an interconnect layer: Layer 7;

FIG. 17 is a plan view illustrating an interconnect layer: Layer 8;

FIG. 18 is a plan view illustrating an interconnect layer: Layer 9;

FIG. 19 is an enlarged view for a matching circuit CT1;

FIG. 20 is an enlarged view for a matching circuit CR1;

FIG. 21 is a plan view illustrating an interconnect pattern of theinterconnect layer: Layer 2:

FIG. 22 is a plan view illustrating an interconnect pattern ofinterlayer layers: Layer 4 and Layer 5;

FIG. 23A is a view illustrating transmission characteristics of adifferential signal line SNDR in a common mode in a case of forming amatching circuit CR1 in a first stage with a through hole and forming amatching circuit CR2 in a second stage with a via;

FIG. 23B is a view illustrating transmission characteristics of adifferential signal line SNDR in a differential mode in a case offorming a matching circuit CR1 in a first stage by a through hole andforming a matching circuit CR2 in a second stage with a via;

FIG. 24A is a view illustrating transmission characteristics of adifferential signal line SNDT in a common mode in a case of forming amatching circuit CT1 in a first stage by a through hole and forming amatching circuit CT2 in a second stage by a via;

FIG. 24B is a view illustrating transmission characteristics of thedifferential signal line SNDT in a differential mode in a case offorming a matching circuit CT1 in a first stage by a through hole andforming a matching circuit CT2 in a second stage by a via;

FIG. 25 is a flow chart showing an outline of a production process ofthe semiconductor device; and

FIG. 26 is a view illustrating an outline of a production process of thepackaging substrate.

DETAILED DESCRIPTION (1) Outline of an Embodiment

At first, an outline of a typical embodiment disclosed in the presentapplication is to be described. Each bracketed reference sign in thedrawing referred to in the outlined explanation of typical embodimentsmerely exemplifies a member or component included in the concept of aconstituent element to which a bracket is attached.

[1] (Semiconductor Device Having a Packaging Substrate in which ThroughHoles and Vias as Matching Circuits are Arranged Each within aPredetermined Range from a Semiconductor Chip)

A semiconductor device according to a typical embodiment of theinvention has a semiconductor chip (2) and an interconnect substrate (1)on which the semiconductor chip is mounted. The interconnect substrate(1) has a first main surface (1 a) on which plural first electrodes (10)electrically connected with the semiconductor chip are formed, a secondmain surface (1 b) opposing the first main surface (1 a), and aninterconnect region interposed between the first main surface (1 a) andthe second main surface (1 b). The first electrode includes plural firstsignal electrodes (10_Rx) and second signal electrodes (10_Tx) forreceiving supply of the signals at a predetermined frequency. The firstsignal electrodes and the second electrodes are arranged being dispersedin the arrangement thereof. The interconnect region has a core substrate(21), plural interconnect layers (20, 22) formed on both surfaces of thecore substrate 21 respectively and plural first through holes (CR1) thatpass through the core substrate for forming an impedance matchingcapacitance. Further, the interconnect region has plural first vias(CT1) that pass through the interconnect layer formed to the coresubstrate on the side of the first main surface for forming impedancematching capacitances. Further, the interconnect region includes pluralfirst signal interconnects (SNR1 to SNRm) connected to the correspondingfirst signal electrode and plural second signal interconnects (SNT1 toSNTn) connected to the corresponding second signal electrode. The firstthrough hole is connected with the first signal interconnect at aposition spaced apart from the first signal electrode by a firstinterconnect length (LR1), and the first via is connected with thesecond signal interconnect at a position spaced apart from the secondinterconnect length (LT1≈LR1) substantially identical with the firstinterconnect length.

With the constitution described above, in the interconnect substrate,plural through holes and vias for impedance matching capacitances(hereinafter referred to as matching circuits) are formed in differentlayers in the interconnection region. Thus more matching circuits can beformed at a higher density compared with a case of forming the matchingcircuits only with the through holes. Further, since the through holesand vias as the matching circuits are formed in different layers,interconnects connected to them respectively can be routed easily tolower the interconnect density. Further, the first vias as the matchingcircuit can be formed by a production process identical with that forusual vias. Therefore, according to the semiconductor device of theinvention, good signal transmission characteristics can be attainedwhile suppressing the manufacturing cost of the interconnect substrate(packaging substrate).

[2] (Matching Circuits Connected in Multi-Stage)

In the semiconductor device described in paragraph (1) above, theinterconnect region further includes plural second through holes (CT2)that pass through the core substrate for forming an impedance matchingcapacitance and plural second vias (CR2) that pass through theinterconnect layer formed to the core substrate on the side of thesecond main surface. The second through hole is connected with thesecond signal interconnect at a position spaced apart from the secondsignal electrode by a third interconnect length (LR2) longer than thefirst interconnect layer and the second via is connected with the firstsignal interconnect at a position spaced apart from the first signalelectrode by a fourth interconnect length (LT2≈LR2) which issubstantially equal with the third interconnect length.

According to the configuration, plural matching circuits are formed tothe first signal interconnect connected to the first signal electrode.In the same manner, plural matching circuits are formed to the secondsignal interconnect connected to the second signal electrode. Thus,signal characteristics can be improved in a wider frequency region.Further, by forming the matching circuit in the second stage connectedto the first signal interconnect by a via and forming the matchingcircuit in the second stage connected to the second signal interconnectby a through hole, matching circuits can be formed at a higher densityand the interconnect density can be lowered.

[3] (Correction Circuit in the First Stage is Formed at a Position Nearλ/4)

In the semiconductor device described in the paragraph (2) above, thefirst interconnect length is a length corresponding to ¼ of anelectromagnetic wave length (λa, λc) corresponding to first frequency(fa, fc) in a signal band required for the signal transmission line.

According to the configuration, distortion of a signal waveform by areflection signal reflected by the first signal interconnect end (secondsignal interconnect end) on the side of the first signal electrode (onthe side of the second signal electrode) can be decreased further.

[4] (Correction Circuit in the Second Stage is Formed at a Position Near3λ/4)

In the semiconductor device described in the paragraph (2) or (3), thethird interconnection length is a length corresponding to ¾ ofelectromagnetic wavelength (λb, λd) in accordance with second frequency(fb, fd) different from the first frequency in the signal band requiredfor the signal transmission line.

The phase of the reflection signal reflected at the matching circuit andreturned to the first signal electrode (second signal electrode) isidentical as π (180 degree) between a case in which the matching circuitis disposed at a position spaced apart by ¼ of the electromagneticwavelength in accordance with the second frequency and a case in whichthe matching circuit is disposed at a position spaced apart by ¾ of theelectromagnetic wavelength from the first signal electrode (secondsignal electrode). Accordingly, the same effect is expected by disposingthe matching circuit at a position of ¾ of the electromagneticwavelength as in the case of disposing the matching circuit at aposition of ¼ of the electromagnetic wavelength. According to thesemiconductor device of the invention, since the matching circuit in thefirst stage (for example, the first through hole) and the matchingcircuit in the second stage (second via) are formed at spaced apartpositions, a region for forming the matching circuit in the second stagecan be ensured easily and the density of the matching circuits can beincreased and the interconnect density can be decreased further. This iseffective when applied, particularly, to a case where the value of thefirst frequency is close to that of the second frequency and it isdifficult to dispose both of the matching circuits in the first stageand the second stage at positions of ¼ of the electromagneticwavelength.

[5] (Correction Circuit in the First Stage is Formed at a Position Near3λ/4)

In the semiconductor device described in the paragraph (2), the firstinterconnect length is a length corresponding to ¾ of theelectromagnetic wavelength (λa, λc) in accordance with the firstfrequency (fa, fc) in the signal band required for the signaltransmission line.

As described above, when the matching circuit is disposed at a positionof ¾ of the electromagnetic wavelength, since the effect identical withthat of the circuit when disposed at a position of ¼ of theelectromagnetic wavelength, distortion of the signal waveform can bedecreased more in the same manner as in the item 3.

[6] (Through Hole and Via do not Overlap)

In the semiconductor device in any one of the items 2 to 5, the firstthrough hole and the first via do not overlap in a plan view.

According to this configuration, interference between the first signalinterconnect and the second signal interconnect by decoupling of thefirst through hole and the first via can be suppressed, therebycontributing to the attainment of good signal transmissioncharacteristics.

[7] (Differential Interconnect Pair)

In the semiconductor device described in any one of the items 2 to 6,the first signal interconnect is a first differential interconnect pairin which two interconnects are formed in parallel (SNDR), and the secondsignal interconnect is a second differential interconnect pair in whichtwo interconnects are formed in parallel (SNDT).

[8] (Tx, Rx)

In the semiconductor device described in any one of the items 1 to 7,one of the first signal electrode and the second signal electrode is areceiving electrode for inputting a signal to the semiconductor chip andthe other of them is a transmitting electrode for outputting a signalfrom the semiconductor chip.

[9] (Shape of Through Hole; Upper/Lower Land Diameters are Different:FIG. 7B)

In the semiconductor device described in any one of the paragraphs (1)to (8), the diameter of the uppermost land and the diameter of thelowermost land connected to the first through hole are different in across sectional view.

According to the configuration, coupling between the first through holeand the interconnect of the upper and lower layers in adjacent therewithcan be decreased, for example, by increasing the diameter of a landadjacent to a layer on the side where the interconnect density is lowand decreasing the diameter of a land adjacent to a layer on the sidewhere the interconnect density is high.

[10] (Shape of Through Hole: Multiple Land; FIG. 7C)

In the semiconductor device described in any one of the items 1 to 8,plural lands are connected in the vertical direction to the firstthrough hole in a cross sectional views.

According to the configuration, since the number of lands that form theparasitic capacitance is increased, the diameter of the land per oneland for obtaining a necessary capacitance value can be decreased, andthe density of the matching circuit can be increased and theinterconnect density can be decreased further.

[11] (Shape of Via: Diameters of Upper/Lower Lands are Different: FIG. 8b, FIG. 8 d)

In the semiconductor device described in any one of the items 1 to 10,the diameter of the uppermost land connected to the first via and thediameter of the lowermost land connected to the first via are differentin a cross sectional view.

According to the configuration, coupling between the first via and theinterconnects of the upper and lower layers adjacent therewith can bedecreased, for example, by increasing the diameter of the land inadjacent to a layer on the side where the interconnect density is lowerand decreasing the diameter of the land adjacent to the layer on theside where the interconnect density is higher.

[12] (Shape of Via: Multiple Land: FIG. 8C, FIG. 8D)

In the semiconductor device described in any one of the items 1 to 10,plural lands are connected to the first via in the vertical direction inthe cross sectional view.

According to the configuration, since the number of the lands that formthe parasitic capacitances is increased, the diameter of the land perone land for obtaining a necessary capacitance value can be decreased,and the density of the matching circuits can be increased and theinterconnect density can be decreased further.

[13] (Via Interconnect: Connected to Identical Interconnect Layer;Combination of FIG. 11A to FIG. 11C)

In the semiconductor device described in any one of the items 1 to 12, aportion of the plural first vias is connected by way of one land to thesecond signal interconnect (FIG. 11B and FIG. 11C), and the remainingportion is connected by way of plural lands to the second signalinterconnect (FIG. 11A).

According to the configuration, since the plural interconnects to beconnected to the respective first vias can be dispersed in pluralinterconnect layers, the interconnect density can be decreased further.

[14] (First Via>Second Via)

In the semiconductor device described in any one of the items 2 to 13,the land diameter of the first via is made larger than that of thesecond via.

The level of the reflection signal reflected at the first signalinterconnect end (second signal interconnect end) on the side of thefirst signal electrode (on the side of the second signal electrode) islower as the distance from the first signal electrode (second signalelectrode) is larger. Accordingly, in the matching circuit in the secondstage formed at a position spaced apart farther from the first signalelectrode (second signal electrode) than the matching circuit in thefirst stage, even when the capacitance value is made smaller than thatin the first stage, a sufficient effect to offset the reflection wavereflected at the first signal interconnect end (second signalinterconnect end) can be obtained. Accordingly, density of the matchingcircuit can be increased and the interconnect density can be decreasedfurther without decreasing the effect of suppressing the distortion ofthe signal waveform by the reflection wave by decreasing the capacitancevalue of the matching circuit in the second stage compared with that ofthe matching circuit in the first stage as in the semiconductor deviceof the invention.

[15] (First Via Larger than Usual Via)

In the semiconductor device described in any one of the items 1 to 14,the diameter of the land of the first via is made larger than that ofthe via for connecting adjacent interconnect layers.

According to the configuration, since the parasitic capacitance of thefirst via is larger than that of the usual via, it can function easilyas the matching circuit.

[16] (Interface Buffer)

In the semiconductor device described in any one of the items 1 to 15,the semiconductor chip has plural interface buffers (Tx1 to Txn, and Rx1to Rxm) which are connected corresponding to the first signal terminaland the second signal terminal respectively.

According to the configuration, signal characteristics of the interfacebuffer can be improved due to the configurations of the items 1 to 15.

[17] (External Terminal: BGA)

The semiconductor device described in any one of the items 1 to 16further has plural external terminals (8). The second main surface hasplural second electrodes (11) electrically connected to thecorresponding external terminals. The first signal interconnect forms atransmission line that electrically connects the first signal electrodeand the corresponding second electrode and the second signalinterconnect forms a transmission line that electrically connects thesecond signal electrode and the corresponding second electrode.

According to the configuration, signal transmission characteristics ofthe transmission line from the semiconductor chip to the externalterminal in the interconnect substrate can be improved.

[18] (Interconnect Substrate]

The interconnect substrate (1) according to a typical embodiment of theinvention has a first main surface (1 a) on which plural the firstelectrodes (10) for electric connection with the semiconductor chip (2),a second main surface (1 b) opposing the first main surface, and aninterconnect region interposed between the first main surface and thesecond main surface. The first electrodes include plural first signalelectrodes (10_Rx) and second signal electrodes (10_Tx) arranged orderlyfor receiving supply of signals at a predetermined frequency. The firstsignal electrodes and the second signal electrodes are arranged beingdispersed in the arrangement thereof. The interconnect region includes acore substrate (21), plural interconnect layers (20, 22) formedrespectively on the both surfaces of the core substrate, and pluralfirst through holes (CR1) that pass through the core substrate forforming an impedance matching capacitance. The interconnect regionfurther includes plural first vias (CT1) that pass through theinterconnect layer (20) formed to the core substrate on the side of thefirst main surface and plural first signal interconnects (SNR1)connected to the corresponding first signal electrodes, and pluralsecond interconnects (SNT1) connected to the corresponding second signalelectrodes. The first through hole is connected to the first signalinterconnect at a position spaced apart from the first signal electrodeby a first interconnect length (LR1), and the first via is connected tothe second signal interconnect at a position spaced apart from thesecond signal electrode by a second interconnect length (LT1)substantially equal with the first interconnect length.

The configuration can provide an interconnect substrate capable ofproviding good signal transmission characteristics while suppressing themanufacturing cost in the same manner as that described in the paragraph(1).

[19] (A Plurality of Matching Circuits to One Signal Interconnect)

In the interconnect substrate described in the item 18, the interconnectregion further includes plural second through holes (CT2) that passthrough the core substrate for forming an impedance matchingcapacitances and plural second via (CR2) that pass through theinterconnect layer formed to the core substrate on the side of thesecond main surface (22). The second through hole is connected to thesecond signal interconnect at a position spaced apart from the secondsignal electrode by a third interconnection length (LR2) which is longerthan the first interconnect length, and the second via is connected tothe second signal interconnect at a position spaced apart from the firstsignal electrode by a fourth interconnect length (LT2) which issubstantially equal with the third interconnect length.

In the same manner as described in the item 2, the configuration canimprove the signal characteristics in a wider frequency band and canincrease the density of the matching circuits and decrease theinterconnect density further.

[20] (Semiconductor Device Having a Packaging Substrate in which ThroughHoles and Vias are Formed being Mixed Together as a Matching Circuit)

A semiconductor device (10) according to a typical embodiment of theinvention has a semiconductor chip (2) and an interconnect substrate (1)on which a semiconductor chip is mounted. The interconnect substrate hasa first main surface (1 a) which is connected electrically to thesemiconductor chip and in which plural signal electrodes for receivingsupply of signals at a predetermined frequency are formed, a second mainsurface (1 b) opposing the first main surface, and an interconnectregion interposed between the first main surface and the second mainsurface. The interconnect region includes a core substrate (21), pluralinterconnect layers (20, 22) formed on both surfaces of the coresubstrate respectively, plural signal interconnects (SNR1 to SNRm, SNT1to SNTn) formed in the interconnect layer and extended from the signalelectrodes, and plural impedance matching circuits connected to thesignal interconnect at a position spaced apart from the signalelectrodes by a predetermined interconnect length (LR1 LT1). A portionof the plural impedance matching circuits is formed of plural throughholes (CR1) that pass through the core substrate and a remaining portionthereof is formed of plural vias (CT1) that pass through theinterconnect layer (20) formed to the core substrate on the side of thefirst main surface.

According to the configuration, since the through holes and vias as theimpedance matching circuit are formed in different layers, it ispossible to form more impedance matching circuits on the interconnectsubstrate compared with a case of forming the impedance matchingcircuits only by the through holes.

[21] (Correction Circuit in the First Stage is Formed to a Position Nearλ/4)

In the interconnect substrate of the item 19, the first interconnectlength corresponds to ¼ of the electromagnetic wavelength (λa, λc) inaccordance with the first frequency (fa, fc) in the signal band requiredfor the signal transmission line.

The configuration can further decrease the distortion of the signalwaveform by the reflection signal reflected at the first signalinterconnect end (second signal interconnect end) on the side of thefirst signal electrode (on the side of the second signal electrode).

[22] (Correction Circuit in the First Stage is Formed to a Position Nearλ/4 and Correction Circuit in the Second Stage is Formed to a PositionNear 3λ/4)

In the interconnect substrate described in the item 21, the thirdinterconnect length corresponds to ¾ of electromagnetic wavelength (λb,λd) in accordance with second frequency (fb, fd) different from thefirst frequency in the signal band required for the signal transmissionline.

According to the configuration, since the matching circuit (for example,first through hole) in the first stage and the matching circuit (secondvia) in the second stage are formed at positions different from eachother, regions for forming the matching circuits in the second stage canbe ensured easily, and the density of the matching circuits can beincreased and the interconnect density can be decreased further. This iseffective in a case, particularly, where the value of the firstfrequency is close to the value of the second frequency and it isdifficult to dispose both of the matching circuits in the first stageand the second stage at the position of ¼ of the electromagneticwavelength.

2. Explanation for the Form of Description, Basic Terms, and Usage inthe Present Application

In the present application, preferred embodiments are described, ifnecessary, being divided into plural sections for the sake ofconvenience. However, they are not independent of each other unlessotherwise specified, but may be each of portions of an example, one maybe details for a portion, a modified example of a portion or the wholeof the other. Further, description for an identical portion is notrepeated as a rule. Further, each of constituent elements in theembodiment is not essential unless otherwise specified, or excluding acase limited theoretically to a specified number and it is apparentlynot so from the context.

Further, in the present application, when “semiconductor device” or“semiconductor integrated circuit device” is referred to, this mainlymeans various kinds of transistors (active devices) per se or thosedevices in which resisters, capacitors, etc. are integrated togetherwith the transistors as the main component on a semiconductor chip, etc.(for example, single crystal silicon substrate), packaged semiconductorchips, etc. Typical examples of various kinds of the transistors caninclude, for example, MISFET (Metal Insulator Semiconductor Field EffectTransistors) typically represented by MOSFET (Metal Oxide SemiconductorField Effect transistors). Typical configuration of the integratedcircuits can include, for example, CMIS (Complementary Metal InsulatorSemiconductor) type integrated circuits typically represented by CMOS(Complementary Metal Oxide Semiconductor) type integrated circuitscomprising N-channel type MISFET and P-channel type MISFET incombination.

Similarly, in the description of embodiments, when it is described as “Xcomprising A” for material, composition, etc., this does not exclude acase comprising other elements than A as one of main constitutionalelements unless otherwise specified, and a case where it is apparentlynot so from the context. For example, when referring to the ingredient,this means “X comprising A as a main ingredient”. For example, when“silicon material” is referred to, this is not restricted only to puresilicon but, needless to say, includes polynary alloys comprisingsilicon as a main ingredient such as SiGe alloy, as well as materialsalso containing other additives, etc.

Similarly, while preferred examples are shown for shapes, positions,properties, etc. it is needless to say that they are not restrictedstrictly thereto unless otherwise specified, and a case where they areapparently not from the context.

Further, when specific numerical value, quantity, or the like isreferred to, the value may be greater than or less than the specifiednumber, unless otherwise specified, or in a case where the number istheoretically limited to the specified number and in a case where it isnot apparently so from the context.

“Wafer” usually means a single crystal silicon wafer on which asemiconductor integrated circuit device (also semiconductor device andelectronic device) is mounted. Needless to say, the wafer also includesepitaxial wafers, and composite wafers comprising insulative substratessuch as SOI substrates and LDC glass.

“Solder” is generally a metal material of low melting temperature (aboutlower than 250° C.) comprising tin as one of main ingredients. Solderincludes “lead-containing solder” that contains lead and “lead-freesolder” that does not contain lead. In the present invention, the solderbump is formed of the lead-free solder as an example.

3. Details of Embodiment

Embodiments of the present invention will be described further indetails. In each of the drawings, identical or similar portions carryidentical or similar symbols or reference numerals, and descriptiontherefor is not repeated as a rule. Further, in the appended drawings,hatchings may sometimes be omitted even for a cross-sectional view in acase where hatching rather makes the drawing complicate or in a casewhere the difference from a vacant portion is clear. In connectiontherewith, even for a hole which is closed in view of a plan view,contours at the background may sometimes be omitted in a case where thisis clear in view of the description or the like. Further, hatchings maysometimes be applied even to a portion of a not cross-sectional view inorder to clearly show that the portion is not a vacant portion.

FIG. 1 is an entire schematic cross sectional view of an electroniccircuit having semiconductor devices according to a first embodiment ofthe present invention mounted thereon.

An electronic circuit 200 illustrated in FIG. 1 is, for example, acircuit module mounted on network equipment such as communicationequipment in a base station of mobile telephones or a router used forhigh speed communication for providing the network equipment with acommunication function. In the electronic circuit 200, pluralsemiconductor devices and various kinds of electronic parts mounted, forexample, on a mounting substrate (printed substrate) 6 such as a motherboard electrically are connected by an interconnect pattern formed inthe mounting substrate 6 and the parts transmit/receive various signalsto between each other thereby providing desired functions. FIG. 1typically illustrates a semiconductor device 100 and anothersemiconductor device 101 as plural parts that form the electroniccircuit 200.

The semiconductor device 100 and another semiconductor device 101 areelectrically connected by way of the mounting substrate 6 andtransmit/receive signals between each other. Although not particularlyrestricted, the semiconductor device 100 has, for example, a storagedevice (memory) for storing data. Further, another semiconductor device101 is, for example, a memory controller which accesses to the memory inthe semiconductor device.

As illustrated in FIG. 1, the semiconductor device 100 includes twosemiconductor chips 2 and 3, plural external terminals 8 formed ofsolder bumps (solder balls), and a packaging substrate (interconnectsubstrate, interposer) 1 on which the semiconductor chips 2 and 3 aremounted. The semiconductor device 100 is, for example, a SIP sealed by aFCBGA (Flip Chip Ball Grid Array) type package in which solder bump toform bump electrodes 7 and 13 are applied to the semiconductor chips 2and 3, and face down-bonded to the packaging substrate 1. The number ofbump electrodes of the semiconductor device 100 illustrated in thedrawing is less than the actual number for the sake of simplifying thedrawing. An actual bump pitch is, for example, about 100 μm for solderbumps on the side of the semiconductor chip (bump electrodes 7, 13) andabout 1 mm for the solder bumps (external terminals 8) on the side ofthe mounting substrate 6. The material for the solder bump preferablyincludes, for example, a silver-added tin type lead-free solder withaddition of 1.5% by weight of silver (melting point; about 221° C.).Various kinds of lead-free solders can be applied in addition to theexample described above. Further, while lead type solder may also beused if the situation allows, use of the lead-free solder is preferredin view of the environment.

FIG. 2 illustrates a detailed entire schematic cross sectional view ofthe semiconductor device 100.

As illustrated in FIG. 2, the packaging substrate 1 has a first mainsurface 1 a formed with plural first electrodes 10 for electricconnection with the semiconductor chips 2 and 3 by way of the bumpelectrodes 7 and 13, a second main surface 1 b opposing the first mainsurface 1 a and formed with plural second electrodes 11 for electricconnection with the external terminals 8, and an interconnect regioninterposed between the first main surface 1 a and the second mainsurface 1 b. The packaging substrate 1 is, for example, a buildupsubstrate. The interconnect region includes, a core substrate 21 andplural interconnect layers (hereinafter also referred to as builduplayers) formed on the both surfaces of the core substrate 21respectively. The core substrate 21 is a glass epoxy substrate having,for example, two interconnect layers, i.e., Layer 5 and Layer 6. In thebuildup layers 20 and 22, an insulation layer (resin) and aninterconnect layer (conductor) are stacked alternately. For example, thebuildup layer 20 formed to the core substrate 21 on the side of thefirst main surface 1 a has four interconnect layers comprising Layer 1,Layer 2, Layer 3, and Layer 4 and the buildup layer 22 formed to thecore substrate 21 on the side of the second main surface 1 b has fourinterconnect layers comprising Layer 7, Layer 8, Layer 9, and Layer 10.As the metal material for the interconnect pattern formed in theinterconnect layers, i.e., Layers 1 to 10, copper (Cu), aluminum (Al),etc. can be used.

The semiconductor chip 3 is, for example, a memory IC. The semiconductorchip 2 is, for example, a logic IC that accesses to the semiconductorchip 3 in accordance with an access demanded from the outside. Thesemiconductor chip 2 writes and reads data to and from the semiconductorchip 3 in accordance with an access from another semiconductor device101. The semiconductor chip 2 includes, for example, a SerDes circuitthat converts serial data and parallel data to each other and performsserial communication, for example, at 12.5 GHz relative to thesemiconductor device 101 and performs parallel communication, forexample, at 1.2 GHz relative to the semiconductor chip 3 by way of theSerDes circuit.

FIG. 3 is a view illustrating a connection relation between thesemiconductor device 100 and another semiconductor device 101.

As illustrated in FIG. 3, the semiconductor chip 2 has plural I/Odevices (interface buffers) as input/output circuits fortransmitting/receiving signals (data) relative to another semiconductordevice 101. Specifically, the semiconductor chip 2 has receiving I/Odevices Rx1 to Rxm (m is an integer of 2 or greater) and a transmittingI/O devices Tx1 to Txn (n is an integer of 2 or greater). In the samemanner, another semiconductor device 101 has plural transmitting I/Odevices XTx1 to XTxm and receiving I/O devices XRx1 to XRxn.

The transmitting I/O devices Tx1 to Txn of the semiconductor device 100are connected respectively to the corresponding I/O devices XRx1 to XRxnof another semiconductor device 101 by way of the external terminals 8of the semiconductor device 100, signal lines SNT1 to SNTn, and theexternal terminals 9 of another semiconductor device 101. In the samemanner, the receiving I/O devices Rx1 to Rxm of the semiconductor device100 are connected to the corresponding I/O devices XTx1 to XTxm ofanother semiconductor device 101 respectively by way of the externalterminals 8 of the semiconductor device 100, the signal lines SNR1 toSNRm and the external terminals 9 of another semiconductor device 101.

The high speed serial communication between the semiconductor device 100and another semiconductor device 101 is performed, for example, by LVDS(Low Voltage Differential Signaling) in which the signal lines SNT1 toSNTn and SNR1 to SNRm form plural differential signal line pairs. Forexample, signal lines SNT1 and SNT2 form a differential signal line SNDTfor high speed serial communication, and the signal lines SNR1 and SNR2form a differential signal line SNDR. In this embodiment, referencenumerals SNR1 to SNRm, SNTR1 to SNTRn, SRDT, and SNDR represent not onlythe signal lines but also transmission lines from the input/outputterminals of the I/O devices of the semiconductor device 100 to theinput/output terminals of the I/O devices of another semiconductordevice 101.

For example, when data are transmitted from the semiconductor chip 2 toanother semiconductor device 101, signals transmitted from thetransmitting I/O devices Tx1 to Txn of the semiconductor chip 2 aresupplied by way of the signal lines SNT1 to SNTn to the I/O devices XRx1to XRxn of another semiconductor device 101. In the same manner, whenthe semiconductor chip 2 receives data from another semiconductor device101, signals transmitted from the I/O devices XTx1 to XTxm of anothersemiconductor device 101 are supplied by way of the signal lines SNR1 toSNRm to the receiving I/O devices Rx1 to Rxm of the semiconductor chip2.

The signal lines SNT1 to SNTn and SNR1 to SNRm are adjusted such thateach of them has 50Ω characteristic impedance and, in accordancetherewith, the transmitting I/O devices Tx1 to Txn and the receiving I/Odevices Rx1 to Rxm of the semiconductor chip 2 are terminated each by aresistance R0 (=50Ω). However, a parasitic capacitance CT0 is present atthe output end of each of the transmitting I/O devices Tx1 to Txn and aparasitic capacitance CR0 is present at the input end of the receivingI/O devices Rx1 to Rxm. Accordingly, as described above, since theadmittance of each of the parasitic capacitance CT0 and CR0 increasesmore as the frequency of the signal supplied to the signal lines SNT1 toSNTn and SNR1 to SNRm is higher, impedance mismatching increases betweenthe I/O devices Tx1 to Txn (Rx1 to Rxm) and the signal lines SNT1 toSNTn (SNR1 to SNRm), tending to cause signal reflection. Then, in thesemiconductor device 100 according to this embodiment, matching circuitsfor impedance matching are formed in the packaging substrate 1.

FIG. 4 is a view illustrating matching circuits formed in the packagingsubstrate 6 of the semiconductor device 100.

In the packaging substrate 6, capacitances are disposed as matchingcircuits for impedance matching to the signal lines SPT1 to SPTn thatconnect the bump electrodes 7 connected respectively to the output endsof the transmitting I/O devices Tx1 to Txn formed in the semiconductorchip 2 and the corresponding external terminals 8.

Specifically, in the packaging substrate 6, capacitances CT1 are formedrespectively at positions spaced apart from the output ends of thetransmitting I/O devices Tx1 to Txn on the signal lines SPT1 to SPTn towhich the output ends of the transmitting I/O devices Tx1 to Txn areconnected (for example, first signal electrodes 10 connected to theoutput ends of the transmitting I/O devices Tx1 to Txn) by ainterconnect length LT1. The interconnect length LT1 is a lengthcorresponding to ¼ of an electromagnetic wavelength λa in accordancewith a first frequency fa in a signal band required for the transmissionlines SNT1 to SNTn. For example, at fa=30 GHz, λa/4 is about 1 mm.According to this configuration, a reciprocal distance of the signal ata frequency of fa when it is outputted from the output end of the I/Odevice Tx1, reflected at the capacitance CT1, and returned again to theoutput end of the I/O device Tx1 is λa/2 (=2×λa/4), for example, in thetransmission line SNT1. Accordingly, since the signal outputted from theoutput end of the I/O device Tx1 returns to the output end of the I/Odevice Tx1 in a state being displaced by π (180 degree) in view of thephase, the reflection wave reflected by the parasitic capacitance CT0 atthe output end of the I/O device Tx1 and the reflection wave reflectedby the capacitance CR1 are offset to each other and the distortion ofthe signal waveform in the transmission line SNT1 can be decreased. Thelength corresponding to ¼ of the electromagnetic wavelength λa is notonly restricted just to the exact interconnect length λa/4 but also moreor less error is permitted relative to the exact interconnect lengthλa/4. For example, a length within range of an error of ±20% relative toλa/4 is permitted. Actually, since the I/O device is not a simplecapacitance or resistance but has a structure of compositing them, anoptimal characteristic cannot sometimes be obtained even when the lengthis set just to the exact interconnect length “λ/4”. In such a case, anoptimal arrangement of the capacitance CT1 may be found whileconsidering the result of simulation and an actually measured value. Asa result, the optimal arrangement of the capacitance CT1 is sometimeswithin the range, for example, from λ/8 to λ/4.

Further, capacitances CT2 as matching circuits are formed each at aposition spaced apart from the output ends of the transmitting I/Odevices Tx1 to Txn by an interconnect length LT2. The interconnectlength LT2 is a length corresponding to ¾ of an electromagneticwavelength λb in accordance with a predetermined frequency fb in asignal band required for the transmission line SNT1. According to theconfiguration, the reciprocal distance, for example, in the transmissionline SNT1, in which a signal at the frequency fb outputted from theoutput end of the I/O device Tx1 is reflected by the capacitance CT2 andreturned again to the output end of the I/O device TX1 is 3λb/2(=2×3λb/4). Accordingly, the reflection wave of the signal outputtedfrom the output end of the I/O device Tx1 returns to the output end ofthe I/O device Tx1 in a state displaced by t in view of the phase in thesame manner as the case that the capacitance CT1 is disposed at aposition spaced apart from the output end of the I/O device Tx1 by ¼ ofthe electromagnetic wavelength. Thus, the reflection wave reflected bythe parasitic capacitance CT0 at the output end of the I/O device Tx1and the reflection wave reflected by the capacitance CT2 offset to eachother and distortion of the signal waveform in the transmission lineSNT1 can be decreased further. The length corresponding to ¾ of theelectromagnetic wavelength kb is not only restricted just to the exactinterconnect length 3λb/4 but a more or less error is permitted relativeto the exact interconnect length 3λb/4 in the same manner as theinterconnect length λa/4 described above. For example, a length withinthe range of an error of ±20% relative to λb/4 is permitted.

In the packaging substrate 6, capacitances as the impedance matchingcircuits are disposed, in the same manner and as the transmission side,to the signal line SPR1 to SPRn which connect the bump electrodes 7connected respectively to the output ends of the receiving I/O devicesRx1 to Rxm formed in the semiconductor chip 2 and the correspondingexternal terminals 8.

Specifically, capacitances CR1 are formed spaced apart each by aninterconnect length LR1 from the input ends of the I/O devices Rx1 toRxm (for example, first signal electrodes 10 connected to the input endsof the I/O devices Rx1 to Rxm) of the I/O devices Rx1 to Rxm on thesignal lines SPR1 to SPRm connected with the input ends of the receivingI/O devices Rx1 to Rxm. The interconnect length LR1 is a lengthcorresponding to ¼ of an electromagnetic wavelength λc in accordancewith a predetermined frequency fc in a signal band required for thetransmission line SNR1. Thus, distortion of the signal waveform in thetransmission line SNR1 can be decreased in the same manner as that inthe transmission line SNT1. Further, capacitances CR2 are formed each ata position spaced apart by an interconnect length LR2 from the inputends of the receiving I/O devices Rx1 to Rxn. The interconnect lengthLR2 is a length corresponding to ¾ of an electromagnetic wavelength λdin accordance with a predetermined frequency fd in the signal bandrequired for the transmission line SNR1. According to the configuration,distortion of the signal waveform in the transmission line SNR1 can bedecreased further in the same manner as in the transmission line SNT1.

In this embodiment, it is assumed that an identical frequency band (12.5Gbps) is required both on the transmission side and the receiving sideof the semiconductor device 100 and that fa=fc (λa=λc) and fb=fd (λb=λd)also for the frequency. Thus, the interconnect length LR1 and theinterconnect length LT1 are substantially made equal, and theinterconnect length LR2 and the interconnect length LT2 are madesubstantially equal. The substantially equal length means not only thejust identical length but also includes a case where a predeterminederror (for example, about ±20%) is present. Further, in the followingdescription, reference sign CT1 represents not only the capacitance butalso a matching circuit formed of the capacitance. This is applied alsoto the reference signs CT2, CR1, and CR2.

FIG. 5A illustrates signal characteristics in a case of disposing amatching circuit CT1 on the signal line SPT1 and FIG. 5(B) illustratessignal characteristics in a case of disposing matching circuits CT1 andCT2 in the signal line SPT1. It is assumed here as: CT1=0.25 pF andC2=0.05 pF.

In FIGS. 5A and 5B, reference numeral 300 shows a return loss of atransmission line SNT1 when none of the matching circuits CT1 and CT2 isdisposed. A reference numeral 301 shows a return loss when a matchingcircuit CT1 is disposed at a position spaced apart from the output endof the I/O device Tx1 by an interconnect length LT1 corresponding to ¼of the electromagnetic wavelength in accordance with a signal frequencyf1 (=12 GHz). Reference numeral 302 shows a return loss when a matchingcircuit CT1 is disposed at a position spaced apart from the output endof the I/O device Tx1 by an interconnect length LT1 corresponding to ¼of the electromagnetic wavelength in accordance with a signal frequencyf1 (=12 GHz) and disposing a matching circuit CT2 at a position spacedapart by an interconnect length LT2 corresponding to ¾ of anelectromagnetic wavelength in accordance with a signal frequency f2 (=8GHz).

As shown by the reference numeral 300, when none of the matchingcircuits CT1 and CT2 is disposed, the return loss increases as thefrequency is higher. On the other hand, as shown by the referencenumeral 301 when the matching circuit CT1 is disposed at a positionspaced apart from the output end of the I/O device Tx1 by aninterconnect length LT1, a bottom of characteristics appears at aposition near 12 GHz. Further, as shown by reference numeral 302 whenthe matching circuit CT2 is disposed at a position spaced apart by theinterconnect length LT2 from the output end of the I/O Tx1 in additionto the capacitance CT1, a bottom of characteristics as the return lossappears at a position near 8 GHz in addition to a position near 12 GHz.By forming plural bottoms of characteristics, return loss can besuppressed in a wide range of the band. Since CT1 >CT2, while themagnitude of the bottom of characteristic near 8 GHz is smaller thanthat near 12 GHz, the return loss can be decreased more by furtherincreasing the matching circuit CT2. Although not illustrated, whencapacitances CR1 and CR2 are disposed in the receiving signal line SPR1of the semiconductor chip 2, signal characteristics show a similar trendas that in FIGS. 5A and 5B.

A specific configuration of matching circuits CT1 and CT2 (CR1 and CR2)is to be described.

In the semiconductor device 100 according to this embodiment, thecapacitances CT1 and CT2 (CR1 and CR2) as the matching circuit areobtained by the parasitic capacitances of through holes or vias in thepackaging substrate 1. The through hole is a through hole that passesthrough the core substrate 21 and the via is a through hole that passesthrough an insulation layer for electrically connecting adjacentinterconnect layers between them in the buildup layers 20 and 22.

FIG. 6 is a schematic view illustrating matching circuits CT1 and CT2(CR1 and CR2) formed in the package substrate 1. As shown in thedrawing, through holes (TH) or vias (Via) are formed each at a positionspaced by a predetermined interconnect length (LT1, LT2, LR1, and LR2)from the input end (output end) of the I/O devices of the semiconductorchip 2. The capacitances CT1, CT2, CR1, CR2 are obtained by utilizingthe parasitic capacitance of the through holes or vias.

As the capacitances CT1, CT2, CR1 and CR2, parasitic capacitances formedmainly between the land connected to the through hole or the via and aground plane formed at the periphery thereof (identical interconnectlayer and upper and lower interconnect layers) is utilized. Accordingly,the capacitance value of each of the matching circuits (capacitance)CT1, CT2, CR1, and CR2 is obtained mainly by adjusting the magnitude ofthe land diameter. For example, the diameter of the land of the via thatforms the capacitance as the matching circuit is made larger than thatof the land of a usual via (via for electrically connecting adjacentinterconnect layers respectively). For example, when the diameter of ausual via is a 90 to 100 μm, the diameter of the via as the matchingcircuit has a larger size. The diameter of the land of the through holethat forms the capacitance as the matching circuit is made identicalwith or optionally larger than that of the land of the usual throughhole (through hole that passes through the core substrate forelectrically connecting the interconnects formed in upper and lowerinterconnect layers respectively).

FIG. 7 and FIG. 8 illustrate examples of shapes of lands connected tothe through hole or the via for forming the matching circuit.

FIG. 7A shows a first example of shape of a land connected to a throughhole that forms the matching circuit, FIG. 7B shows a second example ofshape of the land connected to the through hole that forms the matchingcircuit and FIG. 7C shows a third example of shape of the land connectedto the through hole that forms the matching circuit.

In the first example of shape illustrated in FIG. 7A, diameters of twoupper and lower lands connected to the through hole are made identicalin a cross sectional view of the packaging substrate 1.

In the second example of shape illustrated in FIG. 7B, diameters of theupper and lower lands connected to the through hole are made differentin a cross sectional view of the packaging substrate 1. Thus, couplingbetween the through hole and interconnect in the upper and lower layersadjacent therewith can be decreased by increasing the diameter of theland adjacent to a layer on the side where the interconnect density islower and by decreasing the diameter of the land adjacent to a layer onthe side where the interconnect density is higher. For example, when theinterconnect density is higher on the side of the upper layer than thaton the side of the lower layer of the through hole, as shown in FIG. 7B,the diameter of the land for the upper layer is preferably formed largerthan the diameter of the land for the lower layer.

In the third example of shape illustrated in FIG. 7C, plural lands areconnected in a vertical directions of the through hole in a crosssectional view of the packaging substrate 1. This example of shape isapplicable to a case where the interconnect layer is formed also in theinside in addition to both surfaces of the core substrate 21. FIG. 7Cillustrates a case where two lands are formed in the through holebetween the uppermost land the lowermost land. According to thisconfiguration, the magnitude of the parasitic capacitance formed betweenthe land and the ground plane at the periphery thereof can be controlleddepending on the number of the lands. Accordingly, the diameter of theland per one land for obtaining a desired capacitance value can bedecreased by increasing the number of stages of the lands, and the areaof the region for forming the through hole as the matching circuit canbe made smaller. As shown in FIG. 7B, the diameters of the two uppermostand lowermost lands may be different.

FIG. 8A shows a first example of shape of the land of a via to form amatching circuit, FIG. 8B shows a second example of shape of the landconnected to a via that forms a matching circuit, FIG. 8C shows a thirdexample of shape of the land connected to the via that forms a matchingcircuit, and FIG. 8D shows a fourth example of shape of the landconnected to the via that forms a matching circuit.

In the first example of shape illustrated in FIG. 8A, diameters of twoupper and lower lands connected to the via are made identical in a crosssectional view of the packaging substrate 1.

In the second example of shape illustrated in FIG. 8B, diameters of twoupper and lower lands connected to the via are made different in a crosssectional view of the packaging substrate 1. According to theconfiguration, coupling between the through hole and interconnects inthe upper and lower layers adjacent therewith can be decreased as in thecase of the through hole described above. For example, when theinterconnect density on the side of the lower layer of the via is higherthan that on the side of the upper layer of the via, the diameter of theupper layer land may be formed larger than that of the land of the lowerlayer as shown in FIG. 8B

In the third example of shape illustrated in FIG. 8C, plural lands areconnected in the vertical direction of the via in a cross sectional viewof the packaging substrate 1. FIG. 8C illustrates a case in which oneland is formed between the uppermost and lowermost lands. According tothe configuration, the magnitude of the parasitic capacitance formedbetween the land and the ground plane at the periphery thereof can becontrolled by the number of the lands in the same manner as in thethrough hole described above. Accordingly, the area of the region forforming the via as the matching circuit can be decreased further byincreasing the number of the lands.

In the fourth example of shape illustrated in FIG. 8D, plural lands areconnected in the vertical direction of the via and the diameters of thetwo uppermost and lowermost lands are made different in a crosssectional view of the packaging substrate 1. According to theconfiguration, the area of the region for forming the via as thematching circuit can be decreased further while decreasing couplingbetween the through hole and the interconnects in the upper and lowerlayers adjacent therewith.

FIG. 9 illustrates a plan view of the semiconductor device 100. In thesemiconductor device 100 as illustrated in FIG. 9, a semiconductor chip2 and another semiconductor chip 3 are juxtaposed over the packagingsubstrate 1. A group of interconnects for connecting the semiconductorchip 2 and another semiconductor chip 3 are formed mainly in theinterconnect region of the region B of the packaging substrate 1. Agroup of interconnects connected to the external terminal 8 forconnecting the semiconductor chip 2 and the semiconductor device 101 areformed mainly in the interconnect region of the region A including arange Y from the substrate end P of the packaging substrate 1 to thechip end of the semiconductor chip 2. In the semiconductor device 100,through holes and vias as matching circuits CT1, CT2, CR1, and CR2 areformed, for example, in the region A over the packaging substrate 1.

FIG. 10 illustrates a schematic cross sectional view of the packagingsubstrate 1 in which through holes and vias are formed as matchingcircuits. FIG. 10 typically illustrates a signal line SPT1 that forms adifferential signal line SNDT and matching circuits CT1 and CT2connected to them, and a signal line SPR1 that forms a differentialsignal line SNDR and matching circuits CR1 and CR2 connected to them.For the sake of simplifying the description, the other signal line thatforms the differential signal line and matching circuits connectedtherewith, a via connected to a ground potential, a through holeconnected to the ground potential, etc. are not illustrated.

As illustrated in FIG. 10, a matching circuit CR1 in the first stage ofthe signal line SPR1 on the receiving side of the semiconductor chip 2is formed of a through hole between the interconnect layers, i.e.,between Layers 5 and 6, and a matching circuit CR2 in the second stageis formed of a via between interconnect layers, i.e., between Layers 7and 9. Further, the matching circuit CT1 in the first stage of thesignal line SPT1 on the transmission side of the semiconductor chip 2 isformed of a via between the interconnect layers i.e., between Layers 2and 4, and the matching circuit CT2 in the second stage is formed of athrough hole between interconnect layers, i.e., between Layers 5 and 6.In the signal line SPR1, an interconnect length from the output end(first signal electrode 10_Rx1) of the semiconductor chip 2 to thethrough hole (CR1) in the first stage is LR1, and an interconnect lengthfrom the output electrode (pad) of the I/O device connected to theoutput end (bump electrode 7) of the semiconductor chip 2 to the via(CR2) in the second stage is LR2. In the signal line SNR2, aninterconnect length from the output end (second signal electrode 10_Tx1)of the semiconductor chip 2 to the via (CT1) in the first stage is LT1,and an interconnect length from the output end of the semiconductor chip2 to the through hole (CT2) in the second stage is LT2. The interconnectlength LR1≈LT1 and the interconnect length LR2≈LT2.

As illustrated in FIG. 10, a matching circuit formed of the through hole(CR1) and that formed of the via (CT1) are disposed being mixed togetheras matching circuits in the first stage. According to the configuration,since the matching circuits in the first stage can be formed so as to bestacked in the vertical direction in a cross section of the packagingsubstrate 1, the number of the matching circuits formed on one identicalplane can be decreased to form the matching circuit at a higher densitythan usual compared with a case of forming all of the matching circuitsin the first stage by the through holes. Particularly, when theinterconnect length LR1 and the interconnect length LT1 aresubstantially equal as in this embodiment, since the matching circuitsCR1 and CT1 in the first stage are formed densely at identical positionsin the region A over the packaging substrate 1, more matching circuitscan be formed at a higher density in the region A when the matchingcircuit of the through hole and the matching circuit of the via aredisposed being mixed together as described above. Further, since thematching circuits are formed in the different layers of the interconnectregion of the packaging substrate 1, interconnects connected to therespective matching circuits can be routed easily to decrease theinterconnect density. For example, the signal interconnect after passingthe matching circuit CT1 formed of the via can be routed in the builduplayer 20 on the upper side of the core substrate 21, and the signalinterconnect after passing the matching circuit CT2 formed of thethrough hole can be routed in the buildup layer 22 on the lower side ofthe core substrate 21. That is, since the signal interconnects SPT1 toSPTn and SPR1 to SPRm over the packaging substrate 1 that form thedifferential signal lines SNDR and SNDT can be routed divisionallybetween the upper and the lower interconnect layers of the coresubstrate 21, the density of interconnects formed in one interconnectlayer can be lowered, this can suppress interference betweeninterconnects to each other.

In the same manner, the matching circuit formed of the through hole(CT2) and that formed of the via (CR2) are disposed being mixed togetheras the matching circuits in the second stage. With the configurationdescribed above, the matching circuits in the second stage can be formedat a high density in the same manner as the matching circuits in thefirst stage, and the interconnect density can be lowered. Particularly,in a case where the interconnect length LR2 and the interconnect lengthLT2 are substantially equal as in this embodiment, when the matchingcircuit of the through hole and the matching circuit of the via aremixed together, more matching circuits can be formed at a higher densityin the region A on the packaging substrate 1 in the same manner as thematching circuits in the first stage.

FIGS. 11A to 11C illustrate connection examples of interconnects to viasas matching circuits. FIG. 11A illustrates a first connection example ofan interconnect to a via that forms a matching circuit, FIG. 11Billustrates a second connection example of the interconnect to the viathat forms the matching circuit, and FIG. 11C illustrates a thirdconnection example of the interconnect to the via that forms thematching circuit.

In the first connection example illustrated in FIG. 11A, interconnectsare connected to a via by way of plural lands in a cross sectional viewof the packaging substrate. FIG. 11A illustrates a case in which aninterconnect is connected to the uppermost land to be connected to thevia and another interconnect is connected to the lowermost land to beconnected to the via in the same manner as in the usual connectionmethod of the via and the interconnect.

In the second connection example illustrated in FIG. 11B and the thirdconnection example illustrated in FIG. 11C, interconnects are connectedto the via by way of a single land in a cross sectional view of thepackaging substrate 1. FIG. 11B illustrates a case in which twointerconnects are connected to the lowermost land connected to the via,and FIG. 11C illustrates a case in which two interconnects are connectedto an intermediate land among the lands of three stages connected to thevia.

In any of the connection methods in FIGS. 11A to 11C, the via canfunction as the matching circuit. Further, the connection methods ofFIGS. 11A to 11C can be combined. For example, among the vias that formsplural matching circuits CT1, a portion of the vias is connected to theinterconnects by way of one land as shown in FIGS. 11B and 11C and the aremaining portion of the vias is connected to the interconnects by wayof plural lands as shown in FIG. 11A. According to this configuration,interconnects connected to the via that forms the matching circuit CT1can be routed easily to further increase the density of the matchingcircuits and decrease the interconnect density.

Further, as illustrated in FIG. 10, a via that forms the matchingcircuit CT1 and a through hole that forms the matching circuit CR1 arepreferably disposed so as not to overlap in a plan view. In the samemanner, the through hole that forms the matching circuit CT2 and the viathat forms the matching circuit CR2 are preferably disposed so as not tooverlap in a plan view. This can suppress interference of signalsbetween the through hole and the via by way of the land.

FIG. 12 to FIG. 18 illustrate plan views of respective interconnectlayers corresponding to FIG. 10.

FIG. 12 illustrates a plan view of an interconnect layer: Layer 2, FIG.13 illustrates a plan view of an interconnect layer: Layer 4, FIG. 14illustrates a plan view of an interconnect layer: Layer 5, FIG. 15illustrates a plan view of an interconnect layer: Layer 6, FIG. 16illustrates a plan view of an interconnect layer: Layer 7, FIG. 17illustrates a plan view of an interconnect layer: Layer 8, and FIG. 18illustrates a plan view of an interconnect layer: Layer 9.

As illustrated in FIG. 12 and FIG. 13, in signal lines SPT1 and SPT2that form the differential signal line SNDT on the transmission side ofthe semiconductor chip 2, the matching circuits CT1 disposed in thefirst stage are formed each by a via passing through between theinterconnect layers, i.e., between Layers 2 and 4.

FIG. 19 is an enlarged view of the matching circuit CT1. As illustratedin FIG. 19, two signal lines SNT1 and SNT2 that form a differentialsignal line SNDT are connected to an matching circuit CT1 formed of thevia. Further, plural ground vias 16 connected to a ground potential aredisposed so as to surround each of the vias that form the matchingcircuits CT1 of the differential signal line SNDT. Thus, differentialsignals supplied to the two signal lines SNT1 and SNT2 can be propagatedin the vertical direction of the packaging substrate 1 (verticaldirection in a cross sectional view).

As illustrated in FIGS. 14 and 15, the matching circuits CR1 disposed inthe first stage in the signal lines SPR1 and SPR2 that form thedifferential signal line SNDR on the receiving side of the semiconductorchip 2 are each formed of through holes that pass through theinterconnect layers, i.e., between Layers 5 and 6.

FIG. 20 illustrates an enlarged view of the matching circuit CRT1. Asillustrated in FIG. 20, two signal lines STR1 and SPR2 that form adifferential signal line SNDR are connected to circuits CR1 each formedof a through hole TH. Further, as illustrated in FIG. 20, plural throughholes 15 connected to the ground potential are disposed so as tosurround each of the through holes that form the matching circuits CR1of the differential signal line SNDR. Thus, differential signalssupplied to the two signal lines SNR1 and SNR2 can be propagated in thevertical direction of the packaging substrate 1 (vertical directional ina cross sectional view).

Further, as illustrated in FIG. 14 and FIG. 15, the matching circuitsCT2 disposed in the second stage in the differential signal line SNDT onthe transmission side of the semiconductor chip 2 are formed of thethrough holes that pass through the interconnect layers, i.e., betweenLayers 5 and 6. In the same manner as the matching circuit CR1 describedabove, plural through holes 15 connected to the ground potential aredisposed so as to surround each of the through holes that form thematching circuits CT2 of the differential signal line SNDT.

As illustrated in FIGS. 16 to 18, the matching circuits CR2 disposed inthe second stage in the differential signal line SNDR on the receivingside of semiconductor chip 2 are each formed of vias that pass throughthe interconnect layers, i.e., between Layers 7 and 9. Vias connectedwith the lands formed in the Layer 7, lands formed in the Layer 8, andthe lands formed in the Layer 9 are illustrated as the shape of the viathat forms the matching circuit CR2. Further, in the same manner as thematching circuit CT1 described above, plural ground vias 16 connected tothe ground potential are disposed so as to surround each of the viasthat form the matching circuits CR1 of the differential signal lineSNDR.

The diameter of the land connected to the via that forms the matchingcircuit CR2 in the second stage is made smaller than that of the landconnected to the via that forms the matching circuit CT1 in the firststage. This is determined by considering that the level of the signalreflected by the parasitic capacitances CT0, CR0 at input/output ends ofthe I/O devices Tx1, Rx1, etc. is lowered as it is spaced apart from theinput/output ends of the I/O devices Tx1, Rx1, etc. That is, when thecapacitance value of the matching circuit in the second stage formed ata position spaced apart farther from the I/O devices Tx1, Rx1, etc. thanthe matching circuit in the first stage is made smaller than that in thefirst stage, an effect sufficient to offset the reflection wavereflected at the input/output ends of the I/O devices Tx1, Rx1, etc. canbe obtained. Accordingly, by decreasing the capacitance value of thematching circuit CR2 in the second stage further than that of thematching circuit CT1 in the first stage as described above, an area of aregion for forming the matching circuit CR2 in the second stage can bedecreased. Thus, the density of the matching circuit can be increasedand the interconnect density can be decreased further without reducingthe effect of suppressing the distortion of the signal waveform by thereflection wave.

Further, as illustrated in FIG. 17 and FIG. 18, a mesh-like metalmaterial 30 that absorbs an electromagnetic wave is formed in theinterconnect layer, i.e., Layer 8 just above the opening 31 of thesecond electrode 11 connected to each of external terminals 8. Sincethis can reduce the discontinuity of impedance at the second electrode11 in contact with the external terminal 8 (solder bump), signaltransmission characteristics of the differential signal lines SNDR andSNDT can be improved further.

FIG. 21 and FIG. 22-illustrate an example of an arrangement of thethrough holes and the vias as the matching circuits on the packagingsubstrate 11. In the same manner as in FIG. 10, this example shows acase in which the matching circuits CR1 in the first stage of the signalline SNR1 are formed of through holes between the layers 5 and 6,matching circuits CR2 in the second stage are formed of vias betweenlayers 7 and 9, matching circuits CT1 in the first stage of the signalline SNT1 are formed of vias between the Layers 2 and 4, and thematching circuits CT2 in the second stage are formed of the throughholes between the Layers 5 and 6.

FIG. 21 is a plan view illustrating an example of an interconnectpattern in the interconnect layer, i.e., Layer 2 and FIG. 22 is a planview illustrating an example of an interconnect pattern in theinterconnect layers, i.e., Layers 4 and 5.

As illustrated in FIG. 21, plural first electrodes 10 are formed in aregion just below the semiconductor chip 2 in the packaging substrate 1.Among the plural first electrodes 10, first signal electrodes 10_Rxconnected to the output ends of the transmitting I/O devices Tx of thesemiconductor chip 2, and second signal electrodes 10_Tx connected tothe input ends of the receiving I/O device Rx of the semiconductor chip2 are arranged orderly. For example, as illustrated in FIG. 21, twofirst signal electrodes 10_Rx that form the differential pair aredisposed being juxtaposed in the direction x and, in the same manner,two signal electrodes 10_Tx that form the differential pair arejuxtaposed in the direction x. Then, the differential pair of the firstsignal electrode 10_Rx and the differential pair of the second signalelectrode 10_Tx are arranged alternately on every one set or two sets inthe direction y. The arrangement of the first signal electrodes 10_Txand the arrangement of the second signal electrode 10_Rx are notrestricted to that illustrated in FIG. 21 so long as they are entirelyor partially arranged orderly.

A plurality of the first signal electrodes 10_Rx are arranged asdescribed above and through holes as the matching circuits CR1 areformed each at a position spaced apart by an interconnect length LR1from the respective first signal electrodes 10_Rx. Thus the matchingcircuits CR1 are formed densely in the region S shown in FIG. 21 andFIG. 22.

Further, plural the second signal electrodes 10_Tx are disposed asdescribed above, and vias as the matching circuits CT1 are formed eachat a position spaced apart from each of the second signal electrodes10_Tx by the interconnect length LT1. Thus, the matching circuits CR1are formed densely in a region U shown in FIG. 22. In FIG. 22, theinterconnect length LR1 is made shorter than the interconnect length LT1within a range of an error (within 20%) of an exact interconnect length(λ/4) so that the through hole and the via do not overlap in a planview.

According to FIG. 21 and FIG. 22, it can be understood that morematching circuits are formed at a higher density in the region A overthe packaging substrate 1. Further, it can be understood that a group ofinterconnects connected to the matching circuits are dispersed in pluralinterconnect layers.

FIG. 23A and FIG. 23B illustrate transmission characteristics of thedifferential signal line SNDR in a case where the matching circuit CR1in the first stage is formed of the through hole and the matchingcircuit CR2 in the second stage is formed of the via. The characteristicgraphs are obtained by extracting model parameters from the interconnectpatterns in FIG. 12 to FIG. 18 and performing simulation using the modelparameter by a three-dimensional electromagnetic field simulator.

FIG. 23A illustrates characteristics of a return loss to a signalfrequency in a common mode and FIG. 23B illustrates characteristics of areturn loss to a signal frequency in a differential mode. Referencenumeral 400 represents a required specification value of the return lossin a common mode of the transmission line at 12.5 GHz and referencenumeral 401 represents the return loss of an I/O device RX in the commonmode. Reference numeral 402 represents the return loss of thedifferential signal line SNDR in the common mode when the matchingcircuits CR1 and CR2 are not disposed and reference numeral 403represents the return loss of the differential signal line SNDR in thecommon mode in a case of disposing the matching circuits CR1 and CR2.Further, reference numeral 410 represents a required specification valueof the return loss in the differential mode of the transmission line at12.5 GHz, and reference numeral 411 represents the return loss of theI/O device Rx in the differential mode. Reference numeral 412 representsthe return loss of the differential signal line SNDR in the differentialmode in a case of disposing the matching circuits CR1 and CR2, and areference numeral 413 represents the return loss of the differentialsignal line SNDR in the differential mode in a case of disposing thematching circuits CR1 and CR2.

As can be understood from FIG. 23A and FIG. 23B, good signaltransmission characteristics can be attained in a wide band by disposingthe matching circuits CR1 and CR2 of the differential signal line SNDR.

FIG. 24A and FIG. 24B illustrate transmission characteristics of adifferential signal line SNDT when the matching circuit CT1 in the firststage are formed of vias and the matching circuits CT2 in the secondstage are formed of through holes respectively. The characteristicgraphs are obtained by simulation using extracted model parameters by athree dimensional electromagnetic field simulator in the same manner asin FIG. 23A and FIG. 23B.

FIG. 24A illustrates characteristics of a return loss to a signalfrequency in a common mode and FIG. 24B illustrates characteristics of areturn loss to a signal frequency in a differential mode. Referencenumeral 500 represents a required specification value of the return lossin the common mode of a transmission line at 12.5 GHz and referencenumeral 501 represents the return loss of an I/O device Tx in the commonmode. Reference numeral 502 represents a return loss of the differentialsignal line SNDT in the common mode when the matching circuits CT1 andCT2 are disposed. Further, reference numeral 510 represents a requiredspecification value of the return loss in the differential mode of thetransmission line at 12.5 GHz and the reference numeral 511 representsthe return loss of the I/O device Tx in the differential mode. Referencenumeral 512 represents the return loss of the reference signal line SNDTin the differential mode when the matching circuits CT1 and CT2 aredisposed.

As can be understood from FIG. 24A and FIG. 24B, good signaltransmission characteristics can be attained in a broad band byproviding the matching circuits CT1 and CT2 of the differential signalline SNDT.

A method of manufacturing the semiconductor device 100 is to bedescribed. The semiconductor device 100 is assembled, for example, bythe following sequence.

FIG. 25 is a flow chart showing an outline of a manufacturing process ofthe semiconductor device 100.

While the following example is described specifically referring to aprocess of introducing an underfilling resin after flip chip bonding asan example, it is apparent that the process may comprise mounting of anunderfilling resin before flip chip bonding and, subsequently,performing flip chip bonding.

As illustrated in FIG. 25, semiconductor chips 2 and 3 having bumps areprovided at first (S101). For example, in a solder bump forming steppreceding to the step S101, plural electrode pads (UBM, etc.) are atfirst provided to the device surface of a wafer having a predeterminedcircuit pattern formed therein and solder bumps that form the bumpelectrodes 7 are formed thereon. Then, the wafer is divided intoindividual chips by way of a wafer probe test step, a bump heightinspection step, and a wafer dicing step. Thus, semiconductor chips 2and 3 with bumps are obtained.

Further, a packaging substrate 1 is prepared (S102). The packagingsubstrate 1 is obtained by a manufacturing method of stacking substrateseach by one layer for upper and lower layers in the step ofmanufacturing the interconnect substrate preceding to the step 102 andopening through holes or vias on every stacking to ensure electricconduction. The method of manufacturing the packaging substrate 1 is tobe described specifically later.

Then, the packaging substrate 1 and the semiconductor chips 2 and 3 areelectrically connected by a chip bonding step (flip chip bonding step)(S103). Specifically, in the chip bonding step, electrode pads of thesemiconductor chips 2 and 3 and corresponding first electrodes 10 (firstsignal electrode 10_Rx, second signal electrode 10_Tx, etc.) on thecorresponding packaging substrate 1 are connected by way of the bumpelectrodes 7 by a reflow treatment, for example, at a temperature ofabout 240° C. to 260° C.

Then, an underfilling resin material 12 is injected between the firstmain surface (upper surface) 1 a of the packaging substrate 1 and thedevice surface of the semiconductor chip 2 and a curing process isapplied (S104). Then, the upper surface of the packaging substrate 1 andthe semiconductor chips 2 and 3 are sealed and packaged by a sealingresin material (epoxy) (S105). Then, external solder bumps are attachedas external terminals 8 to the second electrodes 11 of the second mainsurface (lower surface) 1 b of the packaging substrate (S106). Then, thesemiconductor device 100 packaged by the step described above issubjected to a marking step or the like of marking the upper-surface ofthe sealed body and then to a packaging test (S107), and thesemiconductor device 100 passing through a packaging test step ispackaged and shipped after an appearance inspection (S108).

FIG. 26 illustrates an outline of the manufacturing process of thepackaging substrate 1.

As illustrated in FIG. 26, a core substrate 21 in which a copper linedprepreg is bonded to both sides of copper lined plate having aninterconnect pattern formed thereon is prepared (S201). Through holesare opened by drilling the core substrate 21 (S202). In this step,through holes that form the matching circuits (CR1, CT2, etc.) areformed in the same manner as usual through holes. Then, plating(non-electrolytic plating or electrolytic plating) is applied to thethrough holes (S203). Then, buildup layers 20 and 22 are formed. Afterfilling the holes with a resin at first, an interlayer insulation filmis formed on both surfaces (S204). Then, vias are formed by laserfabrication (S205). In this steps, vias that form the matching circuits(CR2, CT1, etc.) are formed in the same manner as usual vias. Further,non-electrolytic copper plating is applied at a level of several μmthickness over the entire surface (S206). Then, a dry film resist ispatterned into an interconnect pattern by using a photomask, andelectrolytic copper plating is applied, for example, at a level of 10 μmthickness in the opened portion (S207). Then, the resist is removed andthe plated copper is lightly etched to form an interconnect (S208).Then, the steps S204 to S208 are repeated thereby forming the builduplayers. After forming a required number of interconnect layers in thebuildup layers, a solder resist is formed as a surface protection film(S209). Then, first electrodes 10 and second electrodes (solder ballpad) 11 are opened as connection portions (pads) to the semiconductorchip 2 and the packaging substrate 1 (S210). Finally, surface treatmentis applied to the opened portions to complete the packaging substrate 1(S211).

As described above, through holes and vias as the matching circuits canbe formed in the same manner as in the case of forming usual throughholes and vias in the packaging substrate 1 and no further steps areadded.

As described above, according to the semiconductor device 100 and thepackaging substrate 1 of the invention, good signal transmissioncharacteristics can be attained while suppressing the manufacturing costof the packaging substrate.

While the invention made by the present inventors has been describedspecifically based on the preferred embodiment, it will be apparent thatthe invention is not restricted only to the embodiment and may bemodified variously within the range not departing the gist of theinvention.

For example, while an embodiment of forming a matching circuit CR1 (CT1)in the first stage at a position of an interconnect length λa/4 has beenillustrated, the invention is not restricted to such an embodiment butthe same effect can be obtained also by forming the matching circuit CR1(CT1) in the first stage at a position of an interconnect length 3λa/4.Further, while an embodiment of forming the matching circuit CR2 (CT2)in the second stage at a position of an interconnect wavelength 3λb/4has been illustrated, the invention is not restricted to such anembodiment, but the same effect can be obtained also by forming thematching circuit CR2 (CT2) in the second stage at a position of aninterconnect length λb/4. For example, in a case where theelectromagnetic wavelengths λa and λb (signal frequencies fa and fb) ofsignals intended to decrease the reflection wave are apart from eachother, the matching circuit in the first stage may be formed at aposition of λa/4 and the matching circuit in the second stage may beformed at a position of λb/4. Alternatively, the matching circuit in thefirst stage may be formed at a position of 3λa/4 and the matchingcircuit in the second stage may be formed at a position of 3λb/4.Further, as the combination of the arrangement of the matching circuitsCT2 and CR2, the following patterns may be considered. For example, thecombination includes a first pattern in which the matching circuit CT2is disposed at a position of an interconnect length 3λb/4 and thematching circuit CR2 is disposed at a position of an interconnect length3λb/4 and a second pattern in which the matching circuit CT1 is disposedat a position of an interconnect length λb/4 and the matching circuitCR2 is disposed at a position of an interconnect length λb/4. Thecombination also includes a third pattern in which the matching circuitCT2 is disposed at a position of an interconnect length 3λb/4 and thematching circuit CR2 is disposed at a position of an interconnect lengthλb/4 or a fourth pattern in which the matching circuit CT2 is disposedat a position of an interconnect length λb/4 and the matching circuitCR2 is disposed at a position of an interconnect length 3λb/4. This isapplicable also to the matching circuits CR1 and CT1. The pattern toform the matching circuit can be changed variously, for example,depending on the electromagnetic wavelengths λa and λb (signalfrequencies fa and fb) of signals intended to decrease the reflectionwave, the margin of the region on the packaging substrate 1, etc. Forexample, when the matching circuits are intended to be disposed denselyin a narrow region, the second pattern may be adopted. When the matchingcircuits are intended to be disposed being dispersed over theinterconnect substrate, the third pattern or the fourth pattern may beadopted.

This embodiment shows an example of using through holes for the matchingcircuits in the first stage using vias for the matching circuits in thesecond stage of the receiving signal line SNDR, using vias for thematching circuits in the first stage, and using through holes for thematching circuits in the second stage of the transmitting signal lineSNDT. However, the invention is not restricted to such configuration.For example, the vias may be used as the matching circuits in the firststage and the through holes may be used as the matching circuits in thesecond stage of the receiving signal line SNDR, and the through holesmay be used as the matching circuits in the first stage and the vias maybe used as the matching circuits in the second stage of the transmittingsignal line SNDT. Further, in a case where the semiconductor device 100has only the transmitting I/O device, it may be configured to use thethrough holes as an the matching circuits in the first stage and use thevias as the matching circuits in the second stage for a portion of thesignal lines and use the vias as the matching circuits in the firststage and use the through holes as the matching circuits in the secondstage for other portion of the signal lines among the pluraltransmitting signal lines connected therewith, and vice versa. This isapplicable also to a case where the semiconductor device 100 has onlythe receiving I/O device.

While the embodiment shows an example in which the matching circuits areformed in two stages to the signal line on the packaging substrate 1,the invention is not restricted to such an example and the number ofstages can be changed in accordance with a required specification. Forexample, the matching circuits may be provided in one stage or in threeor more stages. Also for the matching circuits at or after the thirdstages, the matching circuits may be disposed with reference to λ/4 or3λ/4 in the same manner as in the first stage and the second stage.

While this embodiment illustrates an example of forming the matchingcircuits CR1, etc. on the packaging substrate 1 for impedance matchingof the signal line that connects the bump electrode 7 and the externalterminal 8 in the signal line that connects the semiconductor device 100and another semiconductor device 101, the invention is not restricted tosuch example. For example, for impedance matching of the signal linethat connects the bump electrode 7 of the semiconductor chip 2 and thebump electrode 13 of the semiconductor chip 3, matching circuits can beformed by through holes or vias on the packaging substrate 1 in whichthe signal line is formed.

What is claimed is:
 1. A semiconductor device comprising a semiconductorchip and an interconnect substrate having the semiconductor chip mountedthereon, wherein the interconnect substrate comprises: a first mainsurface formed with a plurality of electrodes connected electrically tothe semiconductor chip; a second main surface opposing the first mainsurface; and an interconnect region interposed between the first mainsurface and the second main surface, wherein the electrodes include aplurality of first electrodes and second electrodes arranged orderly forreceiving supply of signals, and wherein the first electrodes for signaland the second electrodes are disposed being dispersed in thearrangement thereof, and wherein the interconnect region includes: acore substrate; a plurality of interconnect layers formed on bothsurfaces of the core substrate respectively; a plurality of firstthrough holes that pass through the core substrate; a plurality of firstvias that pass through the interconnect layer formed to the coresubstrate on the side of the first main surface; a plurality of firstinterconnects electrically connected with the first electrodes; and aplurality of second interconnects electrically connected to with thesecond electrodes, wherein each first through hole is connected to thefirst interconnect at a position spaced apart from the first electrodeby a first interconnect length, and wherein the first via is connectedto the second interconnect at a position spaced apart from the secondelectrode by a second interconnect length that is substantially equalwith the first interconnect length.
 2. The semiconductor deviceaccording to claim 1, wherein the interconnect region further includes:a plurality of second through holes passing through the core substrate;and a plurality of second vias passing through the interconnect layerformed to the core substrate on the side of the second main surface,wherein each second through hole is connected with the secondinterconnect at a position spaced apart from the second electrode by athird interconnect length longer than the first interconnect length, andwherein each second via is connected with the first interconnect at aposition spaced apart from the first electrode by a fourth interconnectlength that is substantially equal with the third interconnect length.3. The semiconductor device according to claim 2, wherein the firstthrough hole and the first via do not overlap in a plan view.
 4. Thesemiconductor device according to claim 2, wherein the firstinterconnect comprises a first differential interconnect pair formed bytwo interconnects in parallel and the second signal interconnectcomprises a second differential interconnect pair formed by twointerconnects in parallel.
 5. The semiconductor device according toclaim 2, wherein one of the first electrode and the second electrodecomprises a receiving electrode for inputting a signal to thesemiconductor chip and an other of the first electrode and the secondelectrode comprises a transmitting electrode for outputting a signalfrom the semiconductor chip.
 6. The semiconductor device according toclaim 2, wherein the diameter of the uppermost land and the diameter ofthe lowermost land connected to the first through hole are different ina cross sectional view.
 7. The semiconductor device according to claim2, wherein the first through hole is connected with a plurality of landsin a vertical direction in a cross sectional view.
 8. The semiconductordevice according to claim 2, wherein the diameter of the uppermost landand the diameter of the lowermost land connected to the first via aredifferent in a cross sectional view.
 9. The semiconductor deviceaccording to claim 2, wherein a plurality of lands are connected in avertical direction to the first via in a cross sectional view.
 10. Thesemiconductor device according to claim 2, wherein a portion of aplurality of the first vias is connected by way of one land to thesecond interconnect and a remaining portion of the plurality of thefirst vias is connected to the second interconnect by way of a pluralityof lands.
 11. The semiconductor device according to claim 2, wherein thediameter of the land for the first via is larger than that for thesecond via.
 12. The semiconductor device according to claim 2, whereinthe first via has a larger land diameter than that of the adjacent viafor connecting adjacent interconnect layers to each other.
 13. Thesemiconductor device according to claim 2, wherein the semiconductorchip has a plurality of interface buffers connected being correspondedrespectively to the first signal terminal and the second signalterminal.